基于CNFET的三值逐次逼近ADC设计  

Design of Ternary SAR ADC Based on CNFET

作　　者：唐伟童 汪鹏君[1] 王谦[1] 

机构地区：[1]宁波大学电路与系统研究所

出　　处：《华东理工大学学报（自然科学版）》2015年第5期671-676,共6页Journal of East China University of Science and Technology

基　　金：国家自然科学基金(61234002;61274132);浙江省自然科学基金(Z1111219)

摘　　要：模数转换器(Analog-to-Digital Converter,ADC)是片上集成系统的关键部件,通过对逐次逼近逻辑电路和三值逻辑原理的研究,提出了一种基于碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)的三值逐次逼近ADC设计方案。该方案首先控制三值电容阵列的底板电压,逐次逼近其模拟量值,产生由高位到低位的二值信号,然后由编码器将二值转换为三值信号,完成整个转换过程,最后实验证明了所设计的电路逻辑功能正确,并具有明显的高速、低功耗特性。Analog to digital converter （ADC） is a key component in the integrated system-on-chip. By analyzing the successive approximation logic circuits and ternary logic, this paper proposes a designing scheme of ternary successive approximation register （SAR） ADC based on CNFET. Firstly, the ternary capacitor array backplane is supplied to different powers by control circuits. The values of analog is successively approximated so as to produce the corresponding two value signals. Secondly, the encoder transmits two value signals into ternary signal until the end of conversion. The simulation results on HSPICE show that the proposed algorithm has correct logic function, high speed, and low power consumption characteristics.

关 键 词：三值逻辑 CNFET 低功耗 ADC 逐次逼近 

分 类 号：TP332.2[自动化与计算机技术—计算机系统结构]