Impacts of test factors on heavy ion single event multiple-cell upsets in nanometer-scale SRAM  

作　　者：罗尹虹 张凤祁 郭红霞 肖尧 赵雯 丁李利 王园明 

机构地区：[1]State Key Laboratory of Intense Pulsed Radiation Simulation and Effect, Northwest Institute of Nuclear Technology

出　　处：《Journal of Semiconductors》2015年第11期63-68,共6页半导体学报（英文版）

摘　　要：Single event multiple-cell upsets（MCU） increase sharply with the semiconductor devices scaling. The impacts of several test factors on heavy ion single event MCU in 65 nm SRAM are studied based on the buildup of MCU test data acquiring and processing technique, including the heavy ion LET, the tilt angle, the device orientation, the test pattern and the supply voltage; the MCU physical bitmaps are extracted correspondingly. The dependencies of parameters such as the MCU percentage, MCU mean and topological pattern on these factors are summarized and analyzed. This work is meaningful for developing a more reasonable single event test method and assessing the effectiveness of anti-MCU strategies on nanometer-scale devices.Single event multiple-cell upsets（MCU） increase sharply with the semiconductor devices scaling. The impacts of several test factors on heavy ion single event MCU in 65 nm SRAM are studied based on the buildup of MCU test data acquiring and processing technique, including the heavy ion LET, the tilt angle, the device orientation, the test pattern and the supply voltage; the MCU physical bitmaps are extracted correspondingly. The dependencies of parameters such as the MCU percentage, MCU mean and topological pattern on these factors are summarized and analyzed. This work is meaningful for developing a more reasonable single event test method and assessing the effectiveness of anti-MCU strategies on nanometer-scale devices.

关 键 词：multiple-cell upsets nanometer-scale SRAM test factors device orientation 

分 类 号：TN303[电子电信—物理电子学]