Design of high performance and radiation hardened SPARC-V8 processor  

作　　者：赵元富 覃辉 彭和平 于立新 

机构地区：[1]Beijing Microelectronics Technology Institute

出　　处：《Journal of Semiconductors》2015年第11期85-87,共3页半导体学报（英文版）

摘　　要：Design of a highly reliable SPARC-V8 processor for space applications requires consideration singleevent effects including single event upsets, single event transients, single event latch-up, as well as cumulative effects such as the total ionizing dose（TID）. In this paper, the fault tolerance of the SPARC-V8 processor to radiation effects is discussed in detail. The SPARC-V8 processor, fabricated in the 65 nm CMOS process, achieves a frequency of 300 MHz with a core area of 9.78 9.78 mm^2, and it is demonstrated that its radiation hardened performance is suitable for operating in a space environment through the key elements＇ experiments, which show TID resistance to 300 krad（Si）, SEL immunity to greater than 92.5 Me V cm^2/mg, and an SEU error rate of 2.51 10^-4 per day.Design of a highly reliable SPARC-V8 processor for space applications requires consideration singleevent effects including single event upsets, single event transients, single event latch-up, as well as cumulative effects such as the total ionizing dose（TID）. In this paper, the fault tolerance of the SPARC-V8 processor to radiation effects is discussed in detail. The SPARC-V8 processor, fabricated in the 65 nm CMOS process, achieves a frequency of 300 MHz with a core area of 9.78 9.78 mm^2, and it is demonstrated that its radiation hardened performance is suitable for operating in a space environment through the key elements＇ experiments, which show TID resistance to 300 krad（Si）, SEL immunity to greater than 92.5 Me V cm^2/mg, and an SEU error rate of 2.51 10^-4 per day.

关 键 词：PROCESSOR radiation hardening fault-tolerant architecture radiation effects 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]