基于AXI总线的视频数据传输处理的FPGA实现  

Implementation of Video Data Transmission and Processing With FPGA Based on AXI Bus

作　　者：钟雪燕[1] 夏前亮[2] 赵德生[1] 许鹤[1] 

机构地区：[1]南京铁道职业技术学院,南京210031 [2]中电科技德清华莹电子有限公司,浙江湖州313200

出　　处：《计算机测量与控制》2015年第11期3825-3827,共3页Computer Measurement &Control

基　　金：国家自然科学基金面上项目(51475240);航空科学基金自由探索类项目(2014ZD52053)

摘　　要：为了保证铁路视频监控系统实时性,提高视频数据的传输和处理速度,提出了基于AXI总线的视频数据传输处理的FPGA实现;视频数据输入和输出都是XSVI(XILINX streaming video interface)视频格式,传输采用AXI-Stream格式;XSVI2AXI-Stream接口通过触发器将信号同步后,加同步FIFO缓冲转换为AXI-Stream格式;AXI-Stream2XSVI接口通过视频时间控制器产生扫描信号,和AXI-Stream总线传输的视频数据时序对应后得到XSVI格式;XSVI和AXI的转换接口控制器在modelsim软件上实现功能仿真,在ISE软件上实现综合与应用,并在Sparten6开发板上得到验证,AXI总线资源占用较少,同时速率可以达到300 MHz。In order to ensure real-time monitoring system of the railway,improve the transmission and processing speed,a implementation is proposed,which is used to transmit and process video data with AXI bus.The format of input and output video data is XSVI（XILINX Streaming Video Interface）,data transmission uses AXI-Stream format.First trigger signal synchronization,then through synchronous FIFO buffer,XSVI is converted to AXI-Stream format.Time controller module generates scan signals,which is corresponded to video data.The two kinds of signals together mean XSVI format.The function of XSVI and AXI conversion interface controllers is simulated on Modelsim software,synthesized and implemented on the ISE software,and verified on Sparten6 development board,AXI bus occupied with fewer resources,while rates up to 300 MHz.

关 键 词：FPGA AXI XSVI 视频处理 

分 类 号：U29[交通运输工程—交通运输规划与管理] TP39[交通运输工程—道路与铁道工程]