一种用于嵌入式软核的动态可重构容错方案  

A fault-tolerant solution for embedded soft-core processor based on dynamic reconfiguration

作　　者：谭龙生[1] 梁华国[1] 王存[1] 

机构地区：[1]合肥工业大学电子科学与应用物理学院,安徽合肥230009

出　　处：《合肥工业大学学报（自然科学版）》2015年第11期1502-1507,共6页Journal of Hefei University of Technology：Natural Science

基　　金：国家自然科学基金资助项目(61274036;61371025)

摘　　要：FPGA的应用使得电路设计及实现具有更大的灵活性,但同时由于其结构特性,FPGA也更易受到外界的影响,发生瞬态故障,引起软错误。FPGA动态可重构功能的出现及应用为提高FPGA电路设计可靠性提供了一种解决方案。文章提出了一种针对嵌入式软核的重构容错方案,以三模冗余为基础,通过处理器之间的相互控制方法,在实现快速检错的同时,降低了硬件开销及时间开销。The application of field-programmable gate array（FPGA） makes the design and implementation of circuit has greater flexibility. But because of its structural characteristics, FPGA is affected easier by outside, resulting in transient faults and soft errors. The application of FPGA dynamic reconfigurable function provides a solution for improving the reliability of FPGA circuit design. In this paper, a reconfigurable fault-tolerant triple modular redundancy（TMR） based scheme for embedded soft-core processor is presented. The mutual control method between processors is designed and used. The presented scheme can ensure the rapid error detection and reduce hardware and time overhead.

关 键 词：现场可编程门逻辑阵列 可重构 嵌入式 三模冗余 

分 类 号：TN406[电子电信—微电子学与固体电子学]