一种单位增益带宽可调的全差分运算放大器  

A Fully Differential Operational Amplifier with Scalable Unit-Gain Bandwidth

作　　者：杨艳军[1] 曾云[1] 杨洁[2] 

机构地区：[1]湖南大学物理与微电子科学学院,长沙410000 [2]遵义师范学院,贵州遵义563000

出　　处：《微电子学》2015年第6期710-713,717,共5页Microelectronics

基　　金：国家自然科学基金资助项目(61350007)

摘　　要：设计了一种应用于流水线ADC中的全差分增益提升运算放大器。该运放的单位增益带宽受ADC采样速率的控制而自动调节。优化了流水线ADC在不同采样速率下的功耗,提高了ADC的效率。电路采用Chartered 0.18μm CMOS工艺进行设计,Spectre仿真结果表明,当负载为0.5pF、采样率由10MS/s变化到100 MS/s时,运放的单位增益带宽由117.6 MHz变为495.9 MHz,增益由115.2dB下降到98.7dB,相位裕度由78.0°下降到74.1°,运放增益和相位裕度随采样频率的提高略有减小。A fully differential gain-boosted operational amplifier for pipelined ADC was designed. The unit-gainbandwidth of the proposed operational amplifier was scalable with the ADC＇s sampling rate. So the power consumption of the pipelined ADC at different sampling rate could be optimized, and the efficiency of ADC was improved. The operational amplifier was designed in Chartered 0.18 gm CMOS process. The Spectre simulation results showed that the unit-gain bandwidth changed from 117.6 MHz to 495.9 MHz with a capacitive load of 0.5 pF as the sampling rate varied from 10 MS/s to 100 MS/s, while the circuit＇s DC gain and phase margin were reduced slightly. The DC gain was reduced from 115.2 dB to 98.7 dB, and the phase margin was reduced from 78.0° to 74.1°.

关 键 词：全差分运放 单位增益带宽可调 增益提升 共模反馈 

分 类 号：TN432[电子电信—微电子学与固体电子学]