一种基于FPGA的并行H.264/AVC编码器架构  

A Parallel H.264/AVC Encoder Architecture Based on FPGA

作　　者：张建国 关则昂 徐渊[2] 刘劲松[2] 

机构地区：[1]深圳市振华微电子有限公司,广东深圳518060 [2]深圳大学信息工程学院,广东深圳518060

出　　处：《计算机工程》2015年第12期249-255,共7页Computer Engineering

摘　　要：为了提高视频在高性能压缩效率和实时编码方面的性能,提出一种新型的并行处理架构。采用现场可编程门阵列(FPGA)实现整个H.264编码系统设计,包括帧内和帧间预测、变换编码等全部编码过程。针对FPGA的低频工作特点采用高度流水线设计、双缓存机制以及多时域工作等优化处理模式,设计一种快速的宏块匹配预测架构,将图像分辨率设置成可调参数,在Xilinx公司的Virtex-6芯片上应用该硬件系统。测试结果证明,该IP系统在保持较好压缩性能的基础上720P的帧率可达每秒34帧。To deal with the high performance video compression efficiency and real-time playback solutions,a H.264/AVC encoder IP core based on Field Programmable Gate Array（FPGA）is implemented,which contains all the coding process,including both intra and inter prediction,transform-based coding,etc.,and a new type of parallel processing architecture is proposed.To compensate the low-frequency of FPGA chip,high degree of pipeline structure,double-buffers and multi-time-domain are used.Moreover,it also proposes a fast macro-blockmatching predicted architecture,and the video resolution is configurable.The encoder is implemented on the Xilinx Virtex-6 chip,results show that the encoder is able to reach720P34 frames per second with a good compression.

关 键 词：视频编码器 H.264编码 帧内预测 帧间预测 现场可编程门阵列 运动估计 

分 类 号：TP37[自动化与计算机技术—计算机系统结构]