低功耗CMOS带隙基准源  

作　　者：赵玉迎 厚娇 常金[1] 姜久兴[1] 赵波[1] 

机构地区：[1]哈尔滨理工大学

出　　处：《电子世界》2015年第23期27-30,共4页Electronics World

摘　　要：本文采用了CSMC 0.18um的标准CMOS工艺,设计了一种工作在亚阈值区的低功耗CMOS带隙基准源,本设计电路是由纯MOS管组成,不包含双极型晶体管,采用工作在线性区的MOS管代替电阻,减少了芯片的面积,工作在亚阈区的MOS管也使得系统的功耗有所降低。室温下,整个电路系统的电流(包含启动电路)为433.08n A,功耗为649.6n W,版图面积为0.0048mm2,工艺流程与标准CMOS工艺有很好的兼容性。This article uses CSMC 0.18μm standard CMOS process technology, a low power CMOS voltage reference was developed using 0.18μm CMOS process technology, The device consists of MOSFET circuit operated in the subthreshold region and used no resistors, the design of the circuit is composed of pure MOS transistors, does not include the transistors, using a strong-inversion of the MOS transistor instead of resistance, greatly reducing the chip area,working in sub-threshold region MOS transistors also makes the system power consumption is greatly reduced. At room temperature, the current overall circuit （including start-up circuit） is about 433.08nA, the power is 649.6nW, the layout area is 0.0048mm2, process have good compatibility with standard CMOS process.

关 键 词：带隙基准 低功耗 亚阈值区 

分 类 号：TN929.11[电子电信—通信与信息系统]