基于FPGA的Serial RapidIO协议的设计与实现  

Design and implementation of FPGA-based Serial RapidIO protocol

作　　者：许树军[1] 黄镠[1] 牛戴楠[1] 王锐[1] 

机构地区：[1]中国船舶重工集团公司第七二四研究所,南京211153

出　　处：《雷达与对抗》2015年第4期36-38,49,共4页Radar & ECM

摘　　要：在对RapidIO协议和Serial RapidIO(SRIO,下同)IPcore用户接口介绍的基础上,详细描述了Serial RapidIO交换架构在FPGA上的编程方法,并采用双缓存机制实现了位宽、数据流速的转换,完成了多SRIO节点间的高速数据通信,具有较强的通用性和可移植性。The RapidIO protocol and the Serial RapidIO（ SRIO） IPcore user interface（ UI） are introduced,on the basis of which the programming method of the SRIO IPcore exchange architecture on the FPGA is described in detail. The two-stage buffer mechanism is adopted to realize the conversion of the bit width and the data rate and complete the high-speed data communication between multiple SRIO nodes. The RapidIO program features strong generality and portability.

关 键 词：FPGA SRIO IPCORE RAPIDIO 高速通信 串行接口 

分 类 号：TN911.7[电子电信—通信与信息系统]