中国调频频段数字音频广播标准的LDPC编码器设计  

Design of LDPC encoder based on frequency modulation-China digital radio

作　　者：陈冬英[1] 郭里婷[1] 苏凯雄[1] 吴林煌[1] 

机构地区：[1]福州大学物理与信息工程学院,福建福州350116

出　　处：《福州大学学报（自然科学版）》2015年第6期772-777,共6页Journal of Fuzhou University(Natural Science Edition)

基　　金：福建省高校产学合作重大项目(2012H61010016);福建省自然科学基金资助项目(2013J01234)

摘　　要：根据2013年颁布的中国数字音频广播(CDR)中LDPC码的校验矩阵结构特点,提出一种基于生成矩阵的编码方法.该方法将生成矩阵转化为块准循环结构,并行化处理编码算法的行与列操作;采用存储器调用的控制策略,实现CDR标准中四种码率编码,提高了硬件资源的利用率.在Xilinx公司的FPGA平台上进行该编码器的设计,联合Model Sim和Matlab软件进行验证.结果表明,该设计方法具有资源占用较少、功耗低、编码准确率高等特点,其吞吐量约为400 Mbit,达到了CDR标准的LDPC编码要求.According to the structure of LDPC code in frequency modulation- China digital radio（ CDR）,which was promulgated in 2013,a new architecture of generator matrix LDPC coder is proposed. The LDPC code parity matrix structure is exploited to parallelize the row and column encoding operations. An appropriate method is used to control memories,which can reuse memories for different code rates,and improve the utilization of hardware resources. We have implemented the LDPC encoder on Xilinx FPGA. Combining the Model Sim with Matlab simulation results show that the design method has fewer resources consumption,low power,high accuracy rate encoding,and achieves encoding throughput of 400 Mbit. It meets with the requirements of CDR.

关 键 词：中国调频频段数字音频广播 低密度奇偶校验码 编码器 FPGA平台 

分 类 号：TN911.22[电子电信—通信与信息系统]