一种应用于低压差线性稳压器的新型折返限流电路  

Design of a New Foldback Current-Limit Circuit in Low-Dropout Linear Regulator

作　　者：刘晨[1,2] 来新泉[1] 刘从[1] 王宏[2] 张帆[3] 

机构地区：[1]西安电子科技大学CAD研究所 [2]空军工程大学防空反导学院 [3]中国人民解放军空军93861部队

出　　处：《西北工业大学学报》2015年第6期1035-1040,共6页Journal of Northwestern Polytechnical University

基　　金：国家自然科学基金(61106026);中央高校基本业务费(K2014408201)资助

摘　　要：针对大功率负载的电源管理芯片容易出现过载、短路问题,提出一种利用采样电流转化为采样电压的限流模式折返保护电路。该电路限流环路利用缓冲器双支路实现实时控制,其工作状态随输入电压有所转变,hspices仿真实验验证了该电路限流值稳定,基本不随着电源电压的变化而变化,而且芯片的短路功耗降低60%。采用联华电子公司0.5μm 5 V的CMOS工艺线在低压差线性稳压器(LDO)中进行了投片验证,实测芯片常值限流200 mA、折返限流80 mA,自身静态电流极低仅2μA左右。投片测试结果表明,该电路起到保护作用的同时,符合现代电源管理芯片对高效率低功耗的要求。A new circuit that transfer sensing current into sensing voltage under a current bruiting mode with fold- back protection system, is presented in this paper, implemented in 0. 5μm 5V CMOS process and verified by Ca- dence and Hspice simulation. Experimental result verifies that the maximum current limit of the proposed LDO is set to be 200mA, and the foldback current limit is 80μA. Thus, the power consumption of the chip can be saved up to 60% at the foldback circuit condition, which also decreases the risk of damaging the power transistor and makes it widely used in all kinds of power management of microprocessors, moreover, the circuit features simple structure and low quiescent power consumption.

关 键 词：暂态分析 实时控制 电流限制 折返电路 低压差线性稳压器 

分 类 号：TN911.7[电子电信—通信与信息系统]