电荷泵锁相环的相位噪声研究  

Study on phase noise of charge-pump phase-locked loops

作　　者：童姣叶 李荣宽[1] 何国军[1] 

机构地区：[1]电子科技大学电子工程学院,四川成都611730

出　　处：《电子技术应用》2016年第1期28-30,共3页Application of Electronic Technique

摘　　要：传统的计算锁相环相位噪声方法没有考虑热噪声、闪烁噪声及基准噪声等影响因素,且不能较好地对应于实际电路。为了更好地解决这个问题,提出了一种简单的方法先分别计算各影响因素引起的相位噪声,然后获得比较实用的锁相环电路的总相位噪声。该方法使用特殊的叠加理论,统一各影响因素在一个实际的锁相环电路中的相位噪声传递函数,从而得到锁相环的总相位噪声。为了验证提出的计算公式的有效性,用标准的CMOS 0.25μm工艺设计了输出时钟为48 MHz的电荷泵锁相环。仿真结果表明,实现了带内相位噪声低于-88.6 d Bc/Hz,带外相位噪声为-108.4 d Bc/Hz@1 MHz。这些电路仿真结果与理论计算结果基本一致,它们的绝对误差低于2.54 d Bc/Hz。Conventional methods of calculating the phase noise usually can ′ t correspond well with the actual practical circuit without taking into account of thermal noise,flicker noise,shot noise,substrate noise,etc.In order to address the problem,a simple uni-fied method was proposed to calculate the phase noise caused by the affecting factors respectively and then obtain the final total phase noise of an actual practical PLL circuit.The method adopted a special superposition theory to unify all the phase noise trans-fer functions of the affecting factors in a practical PLL circuit.The unification of the transfer functions enables the total phase noise to be obtained by simple calculation.To verify the effectiveness of the derived formula,an output clock of 48 MHz charge-pump PLL is implemented using a standard 0.25 μm CMOS technology.The simulation results show that the in-band phase noise of-88.6 d Bc / Hz and the out-of-band phase noise of-108.4 d Bc / Hz at 1 MHz offset are achieved.These circuit simulation results were correlated very well with the theoretical calculation results with an absolute error of less than 2.54 dBc / Hz.

关 键 词：电荷泵锁相环 传递函数 相位噪声 

分 类 号：TN432[电子电信—微电子学与固体电子学]