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作 者:赵云富[1] 吴一帆[1] 孙强[1] 许娜[1] 吴军[1]
出 处:《微电子学与计算机》2016年第1期1-5,共5页Microelectronics & Computer
摘 要:为了解决SpaceWire总线在进行大数据块收发时,现有的流量控制措施会导致总线性能下降的问题,提出了一种两级存储结构.介绍了SpaceWire总线目前的应用状况,以及存在的问题;通过分析SpaceWire的流量控制机制以及影响总线效率、系统性能的因素,提出了一种能够保证第一级存储器有足够的空间用于收发数据的两级存储结构;根据SpaceWire总线协议和两级存储结构,设计了一款通过硬件预取技术实现大数据块传输的SpaceWire节点IP核;最后在Leon3-FT处理器上集成了该IP核,并进行了系统级的仿真和测试.结果表明,与现有的SpaceWire接口相比,本设计在大数据块传输中能够提高总线效率62.7倍,系统处理效率提高至少14.5倍.To solve the problem of SpaceWire performance degradation,which is caused by the current SpaceWire flow control mechanism when SpaceWire interface transfers the bulk data,a Two-Level memory structure is proposed.The current applications and the existing problems about SpaceWire are introduced.By analyzing the flow control mechanism of the SpaceWire and the factors impacting the bus efficiency and the whole system performance,a Two-Level memory structure,which ensures the first level memory have sufficient space to receive or transfer the bulk data,is proposed.Based on SpaceWire protocol and the Two-Level memory structure,a SpaceWire node IP Core is designed,which can effectively control bulk data transfer through hardware prefetching.Finally,while the IP Core is integrated with the LEON3-FT processor,system level simulation and testing are carried out.The results show that,compared with the conventional SpaceWire node,this design can improve 62.7times in bus efficiency,and at least14.5times in system processing data efficiency when it transfers the bulk data.
关 键 词:SpaceWire总线 流量控制机制 大数据块 两级存储器 硬件预取
分 类 号:TP393.03[自动化与计算机技术—计算机应用技术]
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