多核密码处理器中的片上网络互连结构研究  

Research and Implementation of Network-on-Chip Interlinkage Structure for Multi-core Cipher Processor

作　　者：杜怡然 李伟[1,2] 戴紫彬[1] 

机构地区：[1]解放军信息工程大学,河南郑州450000 [2]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《微电子学与计算机》2016年第1期10-14,共5页Microelectronics & Computer

基　　金：国家自然科学基金(6140417)

摘　　要：为有效解决目前单核密码处理器性能无法满足高速密码运算处理需求的问题,研究了片上网络结构的基本特点,设计并实现了基于共享存储式的簇状片上网络多核密码处理器架构,分析密码运算特征并完成密码算法的多核适配.与单核密码处理器性能相比,本架构有较强的并行性及可扩展性,能够更好地完成大位宽、细粒度密码算法的支持.高效的核间数据交互机制大大提升了片上网络多核密码处理器密码处理性能,能够实现最大426Gb/s的网络数据吞吐量,与通用多核处理器实现密码算法相比,性能提升约5.7%~37.5%.In order to solve the problem that a single-core cipher processor cannot satisfy the high speed cryptographic operations＇ demand,this paper focused on the network-on-chip architecture and proposed a new architecture based on shared memory for multi-core cipher processor.In the proposed architecture,this paper analyzed the characteristic of cryptographic operations and achieved a DES algorithm mapping.Comparing with the single-core cipher processor,the proposed architecture gets a better parallelism and expansibility,to provide a giant bandwidth and fine grit cryptographic algorithm support.An efficient data interaction mechanism is able to improve the performance of multi-core cipher processor,and achieved a maximum throughput for 426 Gb/s. The performance of the proposed architecture improved about 5.7% ~ 37.5% when compared with the general purpose multi-core processor in achieving cryptographic algorithms.

关 键 词：共享存储 片上网络 算法适配 

分 类 号：TN4[电子电信—微电子学与固体电子学]