基于CNFET的三值脉冲式D触发器设计  

Ternary CNFET Pulsed D Flip-flop: Design

作　　者：王谦[1] 汪鹏君[1] 龚道辉 

机构地区：[1]宁波大学电路与系统研究所,浙江宁波315211

出　　处：《宁波大学学报（理工版）》2016年第1期37-41,共5页Journal of Ningbo University：Natural Science and Engineering Edition

基　　金：国家自然科学基金(61234002);浙江省自然科学基金(Z1111219)

摘　　要：通过对脉冲式时序电路的研究,利用多值开关信号理论,设计基于碳纳米场效应晶体管的单边沿和双边沿三值脉冲式D触发器.该方案利用CNFET高速低功耗特征,结合多值逻辑电路的开关运算,简化函数表达式,优化电路结构,减少晶体管数量,达到了降低功耗的目的.经过HSPICE仿真结果表明,所设计的三值脉冲式D触发器具有正确的逻辑功能和低功耗特性.Trigger is the core component in the sequential circuits. Based on exploring the pulsed sequential circuits and the multi-valued switch-signal theory, a design scheme for single-edge and double-edge ternary D flip-flops is proposed using Carbon Nanotubes Field Effect Transistor（CNFET）, which features in high speed transmission and low power consumption. The circuit structure is simplified and the number of transistors needed is reduced by employing multi-valued switching operations. The scheme is simulated using HSPICE, and the results show that the designed ternary pulsed D flip-flop has correct logic function and low power consumption.

关 键 词：三值逻辑 CNFET 脉冲式D触发器 低功耗 

分 类 号：TN783[电子电信—电路与系统]