带参考通道的时间交叉ADC数字后台校准方法  

Background digital calibration method for time-interleaved ADC using A reference ADC

作　　者：陈红梅[1,2] 黄超[2] 邓红辉[2] 尹勇生[2] 林福江[1] 

机构地区：[1]中国科技大学电子科学与技术系,合肥230027 [2]合肥工业大学微电子所,合肥230009

出　　处：《电子测量与仪器学报》2015年第12期1739-1745,共7页Journal of Electronic Measurement and Instrumentation

基　　金：国家自然科学基金面上项目(61076026)资助

摘　　要：设计实现了一种带参考通道的时间交叉ADC(TIADC)通道误差数字后台实时校准方法。参考通道ADC与TIADC各个子通道ADC依次对齐,对同一输入信号在同一时刻进行采样并转换,输出差值被用在数字后台LMS自适应校准算法中以计算通道间的失配误差估计值,实现对各通道失调失配、增益失配和采样时刻失配造成误差的实时校准。FPGA实验结果表明,应用于12 bit,4通道,采样频率400 MS/s的TIADC中,归一化输入频率fin/fs=0.134时,在失调误差、增益误差和采样时钟误差分别为5%FSR、5%和1%Ts条件下,校准后信号噪声失真比(SNR)和无杂散动态范围(SFDR)分别提高了约19.61 d B和28.28 d B,为73.83 d B和86.15 d B,有效位达到11.96位。本校准方法计算复杂度低、易于硬件实现,能够应用于任意通道数的TIADC校准。A background Digital Adaptive Compensation method for channel-mismatches of TIADC using a reference ADC is presented. The background method is performed using a reference ADC synchronously sampling and converting with one of the sub-ADCs of TIADC,and the output difference is used in the adaptive digital calibration algorithm to calculate and compensate channel mismatches of TIADC in real-time. FPGA verification results show that applying in a 4 channel 12 bit 400MS / s TIADC,when normalized input frequency fin/ fs= 0. 134,with 5% full scale range offset mismatch,5% gain mismatch and 1% timing skew mismatch,after calibration,the signal to noise（ SNR） and spurious free dynamic range（ SFDR） improve about 19. 61 d B and 28. 28 d B,and achieve73. 83 d B and 86. 15 d B respectively. The effective number of bits of the TIADC achieves to 11. 96 bits. The calibration method has the merits of low computational complexity,easy hardware implementation,and can be applied to TIADC of arbitrary channel number.

关 键 词：时间交叉模数变换器 高速 通道失配 自适应校准 

分 类 号：TN432.1[电子电信—微电子学与固体电子学]