一种新型低漏功耗数据保持触发器设计  

A Novel Low leakage Power Data-retention Flip-flop Design

作　　者：邬杨波[1] 董恒锋 雷师节 

机构地区：[1]宁波大学信息科学与工程学院,宁波315211

出　　处：《无线通信技术》2015年第4期49-54,59,共7页Wireless Communication Technology

基　　金：国家自然科学基金(61271137);浙江省教育厅科研资助项目(Y201329962)

摘　　要：在无线通信系统中,随着集成电路特征尺寸的不断缩小,芯片漏功耗急剧增大,漏功耗减小技术已成为低功耗无线通信系统设计技术的焦点之一。针对基于功控技术的触发器在休眠状态数据丢失问题,该文提出了一种新型低漏功耗数据保持触发器方案。该触发器使用高阈值的NMOS管作为功控开关以减小触发器休眠期间的漏功耗,使用辅助反相器结合从锁存器中的反相器构成数据存储单元,具有简洁的操作时序。用HSPICE对所设计的触发器进行仿真,结果显示所设计的触发器具有正确的逻辑功能,与传统数据保持触发器相比具有更为简单的操作时序,较低的动态功耗,且休眠漏功耗比传统Mutoh-DFF和DRC-DFF触发器减小了5.6%和24.7%。In the wireless communication system, with the scaling of technology process, leakage power becomes an increasing portion of total power. Power gating technology is an effective method to suppress the leakage power in VLSI design. Regarding to the data loss in the sleep mode, a novel low leakage data retention flip - flop is proposed. A high - Vth NMOS transistor is utilized to reduce the leakage power consumption in the sleep mode. The data retention cell is composed of a pair of always powered cross - coupled inverters in the slave latch. No extra control signals and complex op- erations are needed for controlling the data retention and restoration. The proposed data retention flip -flop is simulated using HSPICE. According to simulation results, the proposed flip -flop has cor- rect logic function, simple operation timing and lower active power. The leakage power of the proposed flip -flop reduces 5.6% and 24.7% compared with the Mutoh -FF and DRC -FF, respectively.

关 键 词：漏功耗 数据保持 功控技术 触发器 

分 类 号：TN402[电子电信—微电子学与固体电子学]