可编程器件的选择性双模冗余加固方法  

A Selective Dual Modular Redundancy Approach for FPGA Hardening Technique

作　　者：郑美松[1,2] 王子龙[1,2] 涂吉[1,2] 王骏也 李立健[1] 

机构地区：[1]中国科学院自动化研究所空天信息中心,北京100190 [2]中国科学院大学,北京100049

出　　处：《计算机辅助设计与图形学学报》2016年第2期355-362,共8页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家自然科学基金(61073035)

摘　　要：针对现有FPGA加固方法开销过大的问题,提出一种利用逻辑门对故障的屏蔽效应进行选择性加固的双模冗余方法.首先建立待加固电路的查找表结构模型,根据故障的传播概率按电路结构依次计算每个查找表的故障敏感度;然后将故障敏感度高的查找表进行双模冗余,并根据要屏蔽的故障类型在冗余后的查找表输出端添加"与","或"逻辑进行表决;最后对加固后的电路进行故障注入,验证加固效果.对MCNC测试集电路的实验结果表明,与现有方法相比,在同等开销下,文中方法对故障的屏蔽效果更显著;全冗余时,该方法可将故障平均减少84.3%,对于apex2,spla等大电路则能减少超过97%.Aiming at the excessive hardware overhead of existing FPGA hardening techniques, this paper pro-poses a selective dual modular redundancy scheme by utilizing the fault masking properties of logic gates to tol-erate faults in FPGAs. Firstly, look up table (LUT) structure circuit model is established for each circuit, and fault sensitivity of each LUT in given circuit is calculated level by level according to fault propagation probability. Se-condly, LUTs with higher fault sensitivity are duplicated, and an AND or OR logic is added to the duplicated LUT output as a voter so that certain faults are masked. Finally, fault injection experiments are carried on the hardened circuits to verify the proposed hardening technique. The experimental results on MCNC test set circuits show that, under the condition of the same overhead, the proposed approach can reduce more faults compared with existing methods. At the full redundant mode, the proposed approach can reduce faults by 84.3% on average, and for large circuits like apex2 and spla can reduce more than 97%.

关 键 词：FPGA 容错 双模冗余 故障敏感度 

分 类 号：TP302.8[自动化与计算机技术—计算机系统结构]