基于FPGA的雷达干扰效果评估接收机设计  

Design of radar jamming effectiveness evaluation receiver based on FPGA

作　　者：李洋[1] 郑辉 

机构地区：[1]哈尔滨工程大学信息与通信工程学院,哈尔滨150001

出　　处：《哈尔滨商业大学学报（自然科学版）》2015年第6期735-740,共6页Journal of Harbin University of Commerce：Natural Sciences Edition

基　　金：中央高校基本科研费专项基金(HEUCF140803)

摘　　要：测试雷达干扰设备性能得到雷达干扰效果评估结果,就要完成加干扰后雷达信号的特征参数提取.介绍了一种基于高速A/D、FPGA、串口组成的雷达干扰效果评估接收机.其接收经过微波前端处理得到的中频信号,通过A/D采样,再利用FPGA系统得到功率、脉宽、带宽时延等参数.信息的测试结果通过串口上报给上位机以完成干扰效果的估计.To gain radar jamming effect evaluation results, characteristic parameter of radar single added interference should be extracted. The jamming effectiveness evaluation receiver was required to receive the IF signal, which was the scrambled radar signal after frequency converting, amplifying, filtering by microwave front -end. Through the high -speed A/D sampling, the FPGA system was able to calculating the signal frequency, power, pulse width, bandwidth, timing and other parameters. Information of the test results reported via a serial port to the PC to complete the interference effect estimates.

关 键 词：FPGA CORDIC 干扰效果评估接收机 

分 类 号：TN972[电子电信—信号与信息处理]