基于FPGA的RS(255,239)译码器的设计与实现  

Design and implementation of RS(255,239) decoder based on FPGA

作　　者：胡雪川 刘会杰[1] 

机构地区：[1]上海微小卫星工程中心,上海201210 [2]上海科技大学信息学院,上海200031

出　　处：《电子设计工程》2016年第1期99-102,共4页Electronic Design Engineering

基　　金：国防科技创新基金(CXJJ-15S086)

摘　　要：为了解决在RS译码中存在的译码过程复杂、译码速度慢和专用译码器价格高等问题,以RS(255,239)码为例,采用了基于改进的无求逆运算的Berlekamp-Massey(BM)迭代算法。结合FPGA平台,利用Xilinx ISE软件和Verilog硬件描述语言,对译码器中各个子模块进行了设计和仿真。整个译码器设计过程采用流水线处理方式。时序仿真结果表明在保证错误符号不大于8个的情况下,经过295个固有延迟之后,每个时钟周期均可连续输出经校正的码字,该RS译码器的纠错能力能够达到预期要求。In order to solve the problem such as the complexity of RS decoding process,low decoding speed, expensive specific RS decoder and so on that exists when the RS code is decoded, the RS（255,239） code is taken as an example,and the RS decoding theory based on the improved non-inversion Berlekamp-Massey（BM） iterative algorithm is introduced.On the FPGA platform, each submodule of the decoder has been designed and simulated by using the Verilog hardware description language and the software of Xilinx ISE 13.4. Pipeline approach is used in the entire decoder design process.Timing simulation results show that if there exists no more than eight errors, after 295 inherent delay, the decoder can output the corrected code word continuously in each clock cycle, and the ability of error correcting of RS decoder meets the expectations.

关 键 词：RS译码器 FPGA 改进型BM算法 流水线 

分 类 号：TN914[电子电信—通信与信息系统]