数字失超探测器时序控制模块的研制  

Design of Timing Control Module Applied to Digital Quench Detector

作　　者：边晓娟[1] 陈福三[1] 龙锋利[1] 程建[1] 张景熙[1] 张敏[1] 

机构地区：[1]中国科学院高能物理研究所中国科学院粒子加速物理与技术重点实验室,北京100049

出　　处：《核电子学与探测技术》2015年第10期1051-1056,共6页Nuclear Electronics & Detection Technology

摘　　要：为了实现超导磁铁的全数字化失超探测,以单个FPGA芯片为控制核心,基于片上集成技术的设计理念,设计了数据采集与时序控制模块。该模块作为整个数字失超探测器的协处理器和主控制器,实现系统的多信道模数转换、数据预处理和缓存及I/O控制,并具有系统软硬件自检功能;与数字信号处理DSP模块协同工作,可以同时对多块超导磁铁实现独立快速的失超探测和报警;并具有良好的灵活性和扩展升级优势,可方便地应用于不同类型超导磁铁的失超探测。文中阐述了时序控制模块的硬件电路设计、FPGA内部的软件功能单元的具体实现方法及实际测试结果。The ADC/Timing Control Module （ADC/TCC） based on the FPGA hardware programmable technique, applied to digital quench detector was designed and implemented. As the coprocessor and main controller of detector, the module performs the multi- channel analog- to- digital conversion, data preprocessing cache and I/O control. In addition, ADC/TCC has the capacity of selfinspection and triggers the quench a- larm signal in case of a quench or failure. Based on the architecture of FPGA and DSP, the system was designed to have fast response, high accuracy, and the capacity of monitoring multiple superconducting magnets simultaneously and raising the alarms separately. The application of programmable technology on - chip makes contribution to the detector＇s integration, flexibility and advantage of upgrading to meet the need of the variety of superconducting magnets in the future accelerator projects. The hardware design and FPGA timing logic software development of ADC/TCC module along with experimental results were expounded in the paper.

关 键 词：失超探测 时序控制 FPGA片上集成 数据采集 超导磁铁 

分 类 号：TL503.8[核科学技术—核技术及应用] TN4[电子电信—微电子学与固体电子学]