A律语音压缩编解码器的FPGA实现  

FPGA Implementation of A-law Speech Compression Encoder and Decoder

作　　者：贾瑞莲[1] 肖沙里[1] 郭成[1] 刘锋[1] 

机构地区：[1]重庆大学光电技术及系统教育部重点实验室

出　　处：《重庆工商大学学报（自然科学版）》2016年第1期59-64,共6页Journal of Chongqing Technology and Business University:Natural Science Edition

基　　金：国家自然科学基金项目(11075226);中央高校基金(CDJZR10120009)资助课题

摘　　要：阐述了A律13折线非线性量化编/解码算法原理,利用Verilog HDL语言在Quartus II软件平台上给出顶层原理图、仿真结果和编/解码部分的关键代码,编/解码器通过现场可编程门阵列(FPGA)下载验证,实现了语音信号的实时传输;实现的过程中利用逐次比较型算法的特点进行了更好的优化和简化,使应用具有更好的可靠性和实时性。This paper expounds the principle of the A-law 13-segment nonlinear quantization encoding/ decoding algorithm. The top floor principle diagram, simulation result and the key code of encoding/decoding part are given by using Verilog HDL language on QuartuslI software platform, and the encoder/decoder can he downloaded and tested via field programmable gate array （FPGA） so that real-time speech signal transmission is implemented.The implementing process is better optimized and simplified based on the characteristics of successive approximation type algorithm so that its application has better reliability and timeliness.

关 键 词：A律 FPGA 编码 解码 

分 类 号：TP321[自动化与计算机技术—计算机系统结构]