10GHz低相噪扩频时钟发生器的设计与实现  

Design and Realization of 10 GHz Low Phase Noise Spread Spectrum Clock Generator

作　　者：曾云[1] 邱玉松 张锋[1] 夏宇[1] 

机构地区：[1]湖南大学物理与微电子科学学院,湖南长沙410082

出　　处：《湖南大学学报（自然科学版）》2016年第2期109-114,共6页Journal of Hunan University:Natural Sciences

基　　金：国家自然科学基金资助项目(61350007);国家高技术研究发展计划(863计划)项目(2011AA010403)~~

摘　　要：基于55nm CMOS工艺设计并制造了一款小数分频锁相环低相噪10GHz扩频时钟发生器(SSCG).该SSCG采用带有开关电容阵列的压控振荡器实现宽频和低增益,利用3阶MASHΔΣ调制技术对电路噪声整形降低带内噪声,使用三角波调制改变分频系数使扩频时钟达到5 000×10^(-6).测试结果表明:时钟发生器的中心工作频率为10GHz,扩频模式下峰值降落达到16.46dB;在1 MHz频偏处的相位噪声为-106.93dBc/Hz.芯片面积为0.7mm×0.7mm,采用1.2V的电源供电,核心电路功耗为17.4mW.A 10 GHz low phase noise spread spectrum clock generator（SSCG） based on a fractional PLL in a 55 nm CMOS process was developed. The clock generator adopts a LC tank voltage-controlled os- cillator （VCO） with switched capacitors array to obtain the wide-band frequency range and low gain, and the multi-stage noise shaping（MASH） modulating technology was utilized to shape and degrade in-band phase noise. The SSCG changes the division ratio with triangular modulation to achieve the goal of 5 000× 10^-1 spread spectrum clock. The measurements show that the clock generator operates at a 10 GHz, the peak reduction of electromagnetic interference （EMI） is 16.46 dB and the phase noise is -106.93 dBc/Hz @1 MHz in Spread Spectrum Clocking （SSC） Mode. The chip core area is less than 0.28 mm2 and the core power consumption is 17.4 mW at a supply of 1.2 V.

关 键 词：扩频时钟发生器 锁相环 ΔΣ调制器 相位噪声 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN74