一种片上低触发电压高耐压NMOS ESD防护结构设计  

An On-chip NMOS ESD Protection Circuit with Low Trigger Voltage and High ESD Robustness

作　　者：陈迪平[1] 刘杏[1] 何龙[1] 陈思园[1] 

机构地区：[1]湖南大学物理与微电子科学学院,湖南长沙410082

出　　处：《湖南大学学报（自然科学版）》2016年第2期115-118,共4页Journal of Hunan University:Natural Sciences

基　　金：湖南省科技计划项目(2014FJ1003)

摘　　要：设计了一种触发电压低于10 V,HBM耐压超过4kV的低触发、高耐压NMOS ESD防护结构.通过带钳位的栅耦合RC网络来适当抬升ESD泄放管栅压与衬底电压.在提高泄放能力与降低触发电压的同时,依然保持了较高的二次击穿电流It,从而增强了MOS防护结构在深亚微米CMOS电路中的ESD防护能力.该结构最终在CSMC HJ018工艺流片,并通过TLP测试平台测得触发电压低于10V,二次击穿电流3.5A,达到设计要求.This paper designed a NMOS ESD protection circuit with low trigger voltage （trigger voltage ≤10 V） and high ESD robustness （HBM ESD level≥4 kV）. It raises the bias voltage of both the gate and the substrate of the main discharge element to an appropriate extent by designing a gate-coupled RC-network with voltage-clamping function. This not only provides a stronger discharge capacity and lower trig- ger voltage but also maintains a high secondary breakdown current. In this case, the ESD robustness of the MOS protection structure in CMOS deep submicron circuit is strengthened. The design is taped out in CSMC HJ018 process, and tested through TLP platform, which shows the trigger voltage is lower than 10 V and the secondary breakdown current is 3.5 A.

关 键 词：ESD 衬底触发 栅耦合 TLP 

分 类 号：TN47[电子电信—微电子学与固体电子学]