一种基于奇偶并行译码架构的高吞吐量译码器设计  

A High-Throughput Decoder based on Architecture of Decoding Odd and Even in Parallel

作　　者：云飞龙 朱宏鹏[1] 吕晶[1] 杜锋[1] 

机构地区：[1]中国人民解放军理工大学,江苏南京210001

出　　处：《通信技术》2016年第3期264-269,共6页Communications Technology

基　　金：国家自然科学基金(No.91338201)~~

摘　　要：针对具有准循环结构的LDPC码,设计了一种高吞吐量译码器。该译码器利用并行分层迭代译码算法,通过校验矩阵同一列循环因子对应的变量节点之间的数据传递更新,实现迭代译码,不仅有效降低了译码时间,同时也省去了变量节点处理单元,另外为了进一步提高吞吐量,针对同一列循环因子都为奇数或偶数的基础矩阵,提出了一种奇偶并行译码架构,该架构一次可同时并行处理2个奇偶变量节点的值,有效节省了一半的译码时间,可将吞吐量提高一倍左右。最后基于Xilinx公司Virtex6系列的xc6vsx475t芯片实现了上述译码器设计,码字采用(3200,1600)LDPC码,经ISE软件环境下布局布线后,结果表明,当迭代次数为15时,译码器吞吐量可达300 Mbps,该研究成果具有重要的实用价值。In connection with QC-LDPC, a high-throughput decoder is designed, which could, with parallel layered decoding algorithm, could enable the variable nodes of the same column circulating factors to correspondingly transmit and update data with each other and realize iterative decoding, thus reducing the decoding time and saving the variable-node disposing unit and the resource. In addition, a new architecture of decoding odd and even in parallel to increase the throughput is proposed and applied to the basic matrix where all of the same columns circulating factors are odd or even. This architecture could decode two variable nodes in parallel, thus to save half time and double the throughput. Finally, the decoder de- sign is implemented on basis of Xilinx Virtex6 xc6vsx475t, and （3200, 1600） LDPC. After the ISE software layout and wiring, the experiment result indicates that the throughput could reach 300Mbps at 15 iterations. This achievement is of important practical value.

关 键 词：并行分层 高吞吐量 QC-LDPC 奇偶并行译码 

分 类 号：TN911.22[电子电信—通信与信息系统]