Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process  

作　　者：Yuan WANG Guangyi LU Haibing GUO Jian CAO Song JIA Xing ZHANG 

机构地区：[1]Institute of Microelectronics, Peking University

出　　处：《Science China(Information Sciences)》2016年第4期108-116,共9页中国科学（信息科学）（英文版）

基　　金：supported by National Basic Research Program of China (Grant No. 2011CBA00606)

摘　　要：A novel, area-efficient transient power-rail electrostatic discharge（ESD） clamp circuit is proposed in this work. Current-mirror capacitors are used to reduce the layout area. Logic threshold voltages of inverters are modified to ensure a fully active on-state for the clamp device in ESD conditions. The proposed circuit reduces the layout area by about 56% compared with a circuit without current-mirror capacitors. Transmission line pulse（TLP） test results based on a 65-nm CMOS process demonstrate that the proposed circuit is an efficient on-chip ESD protection scheme for this process. In addition, the proposed circuit achieves a good immunity to mis-triggering with respect to fast power-up transitions.A novel, area-efficient transient power-rail electrostatic discharge（ESD） clamp circuit is proposed in this work. Current-mirror capacitors are used to reduce the layout area. Logic threshold voltages of inverters are modified to ensure a fully active on-state for the clamp device in ESD conditions. The proposed circuit reduces the layout area by about 56% compared with a circuit without current-mirror capacitors. Transmission line pulse（TLP） test results based on a 65-nm CMOS process demonstrate that the proposed circuit is an efficient on-chip ESD protection scheme for this process. In addition, the proposed circuit achieves a good immunity to mis-triggering with respect to fast power-up transitions.

关 键 词：electrostatic discharge（ESD） power-rail clamp circuit transmission line pulse（TLP） current mirror mis-triggering 

分 类 号：TN432[电子电信—微电子学与固体电子学]