LSB page refresh based retention error recovery scheme for MLC NAND Flash  

作　　者：Haozhi MA Lifang LIU Liyang PAN Jun XU 

机构地区：[1]Institute of Microelectronics, Tsinghua University, Beijing 100084, China [2]Tsinghua National Laboratory for Information Science and Technology, Beijing 100084, China

出　　处：《Science China(Information Sciences)》2016年第4期117-127,共11页中国科学（信息科学）（英文版）

基　　金：supported by National Basic Research Program of China (973) (Grant No. 2011CBA00602);National Key Scientific and Technological Project (Grant No. 2013ZX01032001-001);National Natural Science Foundation of China (Grant No. 61106102)

摘　　要：NAND Flash memories present inevitable decline in reliability due to scaling down and multilevel cell（MLC） technology. High retention error rate in highly program/erase（P/E） cycled blocks induces stronger ECC requirement in system, causing higher spare bits cost and hardware overhead. In this paper, a least significant bit（LSB） page refresh based retention recovery scheme is proposed to improve the retention reliability of highly scaled MLC NAND Flash. As in the scheme, LSB page refresh operation induces floating gate electron re-injection to compensate charge leakage during long retention time, and realizes retention error rate reduction. Experiment result on 2x-nm MLC NAND Flash exhibits more than 78% retention error rate reduction. Compared with reported retention error recovery scheme, the proposed scheme presents 2.5 times recovery efficiency promotion and 60% latency reduction.NAND Flash memories present inevitable decline in reliability due to scaling down and multilevel cell（MLC） technology. High retention error rate in highly program/erase（P/E） cycled blocks induces stronger ECC requirement in system, causing higher spare bits cost and hardware overhead. In this paper, a least significant bit（LSB） page refresh based retention recovery scheme is proposed to improve the retention reliability of highly scaled MLC NAND Flash. As in the scheme, LSB page refresh operation induces floating gate electron re-injection to compensate charge leakage during long retention time, and realizes retention error rate reduction. Experiment result on 2x-nm MLC NAND Flash exhibits more than 78% retention error rate reduction. Compared with reported retention error recovery scheme, the proposed scheme presents 2.5 times recovery efficiency promotion and 60% latency reduction.

关 键 词：NAND flash reliability retention refresh data error recovery 

分 类 号：TP333[自动化与计算机技术—计算机系统结构] TP316.7[自动化与计算机技术—计算机科学与技术]