A 2.5 GS/s 14-bit D/A converter with 8 to 1 MUX  

作　　者：张俊安 李广军 张瑞涛 付东兵 李皎雪 魏亚峰 阎波 刘军 李儒章 

机构地区：[1]Collage of Communication and Information Engineering, University of Electronic Science and Technology of China, Chengdu 611731, China [2]Key Laboratory of Analog Integrated Circuit, Chongqing 400060, China [3]Chongqing Acoustic-Optic-Electronic CO. LTD, Chongqing 401332, China

出　　处：《Journal of Semiconductors》2016年第3期95-102,共8页半导体学报（英文版）

基　　金：Project supported by the National Natural Science Foundation of China(Nos.61006027,61176030);the Research Foundation of Key Laboratory of Analog Integrated Circuit(Nos.9140C0902120C09034,9140c090204130c09042);the Fundamental Research Funds for the Central Universities of China(No.ZYGX2012J003)

摘　　要：A 2.5 GS/s 14-bit D/A converter（DAC） with 8 to 1 MUX is presented. This 14-bit DAC uses a ＂5＋9＂segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT（process, source voltage and temperature） corner is also presented. The8 to 1 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. A DEM function which is merged with a ＂5-31＂decoder is used to improve the DAC＇s dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer（DDS） chip, and is implemented in a 0.18 m CMOS technology, occupies 4.86 2. 28 mm-2 including bond pads（DAC only）, and the measured performance is SFDR 〉 40 d B（with and without DEM） for output signal frequency up to 1 GHz. Compared with other present published DACs with a non-analog-resample structure（means return-to-zero or quad-switch structure is unutilized）,this paper DAC＇s clock frequency（2.5 GHz） and higher output frequency SFDR（〉 40 d B, up to 1 GHz） has some competition.A 2.5 GS/s 14-bit D/A converter（DAC） with 8 to 1 MUX is presented. This 14-bit DAC uses a ＂5＋9＂segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT（process, source voltage and temperature） corner is also presented. The8 to 1 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. A DEM function which is merged with a ＂5-31＂decoder is used to improve the DAC＇s dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer（DDS） chip, and is implemented in a 0.18 m CMOS technology, occupies 4.86 2. 28 mm-2 including bond pads（DAC only）, and the measured performance is SFDR 〉 40 d B（with and without DEM） for output signal frequency up to 1 GHz. Compared with other present published DACs with a non-analog-resample structure（means return-to-zero or quad-switch structure is unutilized）,this paper DAC＇s clock frequency（2.5 GHz） and higher output frequency SFDR（〉 40 d B, up to 1 GHz） has some competition.

关 键 词：PMOS current-steering D/A converter bias circuit high speed MUX dynamic element match（DEM） 

分 类 号：TN792[电子电信—电路与系统]