基于高速DDFS的高精度DAC的设计  

Design of DDFS-Based High Accuracy Digital-to-analog Converter

作　　者：张涛[1] 万书芹[1] 苏小波[1] 于宗光[1] 

机构地区：[1]中国电子科技集团公司第58研究所,江苏无锡214035

出　　处：《中国电子科学研究院学报》2015年第6期632-635,共4页Journal of China Academy of Electronics and Information Technology

基　　金：333高层次人才培养工程专项资助(2007124);广东省部产学研合作引导项目资助(2009B090300416)

摘　　要：设计了一种应用于高速数字频率合成器的高精度DAC。电路采用6+8分段式电流舵结构进行设计,高6位为温度计编码,低8位为二进制编码,设计中采用Q^2旋转漫游算法排布电流源阵列,双路归零编码控制输出。基于SMIC 0.13μm 1P6M数模混合CMOS工艺设计实现,芯片面积2.66×2.54 mm^2,测试结果积分非线性误差INL≤1.5 LSB,微分非线性误差DNL≤0.8 LSB,在1GHz时钟采样频率,401 MHz输出频率处,SFDR为88 dBc。An embedded 14-bit 1-GS/s digital-to-analog converter（DAC） for Direct Digital Frequency Synthesizer（DDFS） application is presented.The DAC is implemented using a segmented current-steering architecture,with the top 6bits and the remaining 8 bits.It uses the novel Q2 Random Walk switching scheme to obtain reduce tuning.The output stage of dual return-to-zero scheme is used to enhance the dynamic performance of spurious-free dynamic range（SFDR）.The DAC core is fabricated in a 1P6M0.13 um 1P6M standard CMOS technology,occupies a die area of only 2.66×2.54 squared mm.The measured differential non-linearity lies between-0.8 LSB and 0.8LSB,integral non-linearity lies between- 1.5LSB and 1.5LSB.And the SFDR is 88 dB at 401 MHz output of 1GHz sampling clock rate.

关 键 词：数模转换器 电流舵 双路归零 INL、DNL 

分 类 号：TN4[电子电信—微电子学与固体电子学]