一种基于FPGA的微波时钟恢复的设计与实现  

Design and implementation of microwave clock recovery based on FPGA

作　　者：张丽[1] 徐妍[1] 马丽珍[1] 

机构地区：[1]中兴通讯股份有限公司上海研发中心,上海201203

出　　处：《微型机与应用》2016年第5期81-83,共3页Microcomputer & Its Applications

摘　　要：在微波通信系统中,受天气情况的影响,发送端的时钟频率可能随时变化。在接收端如何进行时钟恢复是微波通信的难点。本文给出了一种基于FPGA的微波无线口时钟恢复的设计。该设计使用FPGA内的PLL和FIFO,实时调整时钟频率,保证接收端恢复时钟的频率与发送端无线口的发射时钟信号频率一致,且减少了PLL个数,避免了PLL失锁及其引发的复位重新锁定过程。In the microwave telecommunication system,the sender clock is changing in anytime. Clock recovery in receirer is the difficulty of microwave telecommunication. In this paper,we introduce a FPGA design of microwave telecommunication clock recovery. This design utilizes FPGA internal PLL and FIFO cores,which can adjust clock frequency instantly,ensure the receiver＇s recovered clock have the same frequency with the sender clock. It also reduces the number of PLLs,and avoids the process of PLL re- lock after the PLL losing lock.

关 键 词：微波通信 时钟恢复 FPGA PLL 

分 类 号：TN925.9[电子电信—通信与信息系统]