FPGA模型设计与手写代码资源效率的研究  

FPGA Model Design and Resource Efficiency of Handwritten Code

作　　者：邢玉磊 赵刚[1] 

机构地区：[1]四川大学电子信息学院,四川成都610065

出　　处：《通信技术》2016年第4期504-508,共5页Communications Technology

摘　　要：为了进一步研究FPGA开发工具DSP Builder基于模型设计的实用性。通过两种方法创建了基于M序列的2ASK调制解调系统:一种是在DSP Builder中利用模块进行建模的方法,通过自动生成HDL代码,下载到由南京润众科技有限公司提供的RZ8681现代通信技术试验平台上的FPGA硬件仿真模块中,并由安捷伦示波器测出了系统中的信号,对建模过程中的硬件资源利用率进行了记录;另一种通过手写VHDL代码实现了该系统,也记录了系统编译后所消耗的资源。对比两种方法,得出了基于DSP Builder的模型设计可以很好地提高在FPGA上开发DSP的效能,是一种很实用的工具。To further investigate the practicality of FPGA development tools by DSP Builder based on model design, 2ASK modem system based on the M sequence is constructed in two methods. And for one meth- od, the module in the DSP Builder is used to anstruct the model, through automatically generating HDL code, and downloaded into FPGA hardware simulation module on RZ8681, a modern communication tech- nology test platform provided by Nanjing Runzhong Sci. ＆Tech. Co. , Ltd. The signal of the system is measured with Agilent oscilloscope, and the utilization of hardware resource in the modeling process also re- corded. For the other method 2ASK modem system is implemented by writing VHDL code, and the re- source comsumption after compiling also recorded. The comparison of these two methods indicates the mod- el design based on DSP Builder could improve the effectiveness of DSP development on FPGA, and this model is a very practical tool.

关 键 词：DSP BUILDER 二进制幅移键控 M序列 现场可编程门阵列 手写代码 资源效率 

分 类 号：TN311[电子电信—物理电子学]