基于端系统应用的分组I/O加速技术  

Packet I/O acceleration technology based on terminal system application

作　　者：李世星[1] 杨惠[2] 龙永新[1] 刘三毛[1] 

机构地区：[1]湖南工业大学计算机与通信学院,湖南株洲412000 [2]国防科学技术大学计算机学院,湖南长沙410073

出　　处：《微型机与应用》2016年第7期63-66,共4页Microcomputer & Its Applications

基　　金：国家自然科学基金(61170102)

摘　　要：在网络系统中,优化端系统的数据路径能够使数据在网络接口和应用程序之间快速移动。因此,研究基于端系统应用的分组I/O加速技术,对分组I/O的发送和接收路径分别优化,有助于提高数据移动效率,减少CPU停滞,实现内存并行处理。本文提出分组I/O接收端流亲和技术,分组I/O发送端链式发送技术。基于通用多核处理器和FPGA搭建端系统实验环境,并对分组I/O加速后的端系统进行性能测试,实验结果表明,采用分组I/O加速技术的端系统,能够使报文收发性能提升2.14倍。In network system, studying on acceleration technology based on packet I/O for terminal system application, optimizing the transfer data paths of packet I/O, will improve the data transfer rate between network interface and program space of user application, reduce the CPU stall and realize high efficient parallel processing. In this paper, we use streaming affinity technology for the packet I/O receiver, and use the chain transmission technology in the packet I/O sender. We develop a common platform with muhicore processor and FPGA for terminal sys- tem, and make some experiments on sending and receiving packet performance with packet I/0 acceleration technology. The experimental re- suits show that the proposed scheme can achieve to 2.14x packet throughput.

关 键 词：端系统 多核 数据路径 FPGA 

分 类 号：TP393.0[自动化与计算机技术—计算机应用技术]