高速图像采集系统中的SDRAM缓存模块设计  

SDRAM Cache Design of High-speed Image Acquisition System

作　　者：程光伟[1] 陈玲玲[1] 

机构地区：[1]西安工业大学电子信息工程学院,西安710021

出　　处：《计算机与数字工程》2016年第3期538-541,共4页Computer & Digital Engineering

摘　　要：在数字视频图像采集及其实时显示系统中,由于前端传感器采集速度过快,一般与后端显示系统时钟不匹配,大量的数据需要先进行缓存再输入给后端的显示模块。针对以上问题,在研究SDRAM原理和时序的基础上,采用verilog语言,成功实现基于FPGA的SDRAM控制器设计,同时利用FIFO缓存数据很好地解决了前端数据采集和后端视频显示异步时钟域的数据交换问题,实现了SDRAM缓存数据的功能。论文详细介绍各模块的原理和实现方法,实验仿真及结果表明,设计实现的SDRAM双端口控制器,具有电路简单、工作可靠等优点,封装后可以应用在别的视频图像采集系统的项目中,可缩短开发周期。In the digital video image acquisition and real-time display system,since the front sensor collects too fast,usually with back-end display system clock does not match the amount of data you need to re-enter the cache to the backend of the display module.To solve these problems,on the basic research of principles and timing of SDRAM,using verilog language,the successful implementation of FPGA-based controller design of SDRAM,while taking advantage of a good solution to data FIFO buffer data acquisition front-end and back-end video display asynchronous clock domains data exchange problem,the function of SDRAM cache data is realized.Details are presented below principles and implementation methods,simulation and experimental results show that each module,SDRAM dual-port controller design implemented with a simple circuit,reliable work,etc.,can be applied in the project after the package other video image acquisition system,the development cycle can be shorten.

关 键 词：FPGA技术 SDRAM控制器 FIFO缓存 异步时钟 跨时钟域传输 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]