高动态BDS/GPS联合接收机基带芯片设计与实现  

Design and Implementation of Baseband ASIC for High Dynamic BDS/GPS Combined Receiver

作　　者：侯冰[1] 张晓林[1] 郭九源[1] 赵雷[1] 

机构地区：[1]北京航空航天大学电子信息工程学院,北京100191

出　　处：《遥测遥控》2016年第1期11-20,共10页Journal of Telemetry,Tracking and Command

基　　金：国防科工委航天民用专项;北京重点学科基金资助项目(No.XK100060525)

摘　　要：提出一种适用于高动态BDS/GPS联合接收机的基带芯片结构设计,主要包括兼容BDS/GPS的通用C/A码发生器模块、载波NCO模块、码NCO模块和捕获跟踪通道支路结构的设计。该设计可以节约硬件资源,提高卫星信号捕获速度和接收机动态范围。在软件仿真和FPGA原型验证的基础上,设计实现了一款BDS/GPS联合接收机基带芯片,实际样片测试结果验证了设计的有效性。A novel architecture of baseband ASIC for high dynamic BDS/GPS combined receiver is proposed. The design of general C/A code generator, carrier NCO, code NCO and architecture of acquisition and tracking channel, which is compatible with dual systems of BDS and GPS, is discussed in detail. The proposed architecture can decrease the acquisition time and improve the receiver＇ s dynamic range at low hardware cost. Based on the software simulation and FPGA prototype, a baseband ASIC is devel- oped. The above - mentioned design is fully verified by actual test results.

关 键 词：北斗卫星导航系统 基带芯片 捕获跟踪 高动态 

分 类 号：TN967.1[电子电信—信号与信息处理]