基于FPGA视频合成系统设计与实现  

Design and Implementation of Video Synthesis System Based on FPGA

作　　者：董青[1] 朱洪翔[1] 祁晓鹏 

机构地区：[1]中国飞行试验研究院,西安710089

出　　处：《计算机测量与控制》2016年第4期247-249,共3页Computer Measurement &Control

摘　　要：为实现将输入的六路BT656视频无失真地合并成一路BT1120视频输出,采用将FPGA技术和视频合成系统相结合的设计方法,用verilog语言设计完成有效视频数据的抽取、SRAM乒乓操作以及FPGA对于视频的拼接处理方法;该系统由视频输入解码模块、存储模块、输出解码模块、I2C模块以及时钟管理模块组成;经算法仿真和逻辑综合,该设计可以实现视频合成的基本功能,满足视频监控系统的实时性要求.综合结果表明该设计占用FPGA片上逻辑资源少,系统运行频率高。The paper presents a design of eompositing 6 channels of BT656 input video to one BT1120 output video undistorted by combining FPGA and video compositing system. Achieve the video data extraction, SRAM ping-pong operation and video splicing method by Verilog language. The video compositing system consists of video input decoding module, memory module, the output decoding module, I^2C module and clock management module. After algorithm simulation and logic synthesis, the design can achieve the basic functions of video composition; meet the requirement of real-time video surveillance system. By the combined results we can know that this design occupied considerably less logic resources in the FPGA chip, and the entire design can run with very high frequency.

关 键 词：FPGA 视频合成 VERILOG 实时性 

分 类 号：TB114.3[理学—概率论与数理统计]