阵列探测器L1触发系统加法电路优化设计  

A Design of Adder-Module Circuit for the L1 Trigger System of Array Detector

作　　者：张晰[1,2] 千奕[1] 王晓辉[1] 李良辉[1,2] 杨振雷[1,2] 苏弘[1] 

机构地区：[1]中国科学院近代物理研究所,兰州730000 [2]中国科学院大学,北京100049

出　　处：《核电子学与探测技术》2015年第12期1212-1215,共4页Nuclear Electronics & Detection Technology

基　　金：国家自然科学基金(11475233;11305233)资助

摘　　要：针对兰州重离子加速器外靶终端硅微条阵列探测器L1触发系统,设计了一个基于Xilinx7系列FPGA芯片的改进加法逻辑电路,利用快速进位链结构,对加法电路模块进行优化。对优化后加法电路结构和同类传统加法电路比较,并对逻辑时延进行和结构性能建模分析。仿真和测试结果表明:优化后模块逻辑时延3 ns左右,相比传统加法逻辑,系统死时间低,有效采集事例率高,能够满足L1触发系统的要求。Focused on the level 1 sub - trigger system in Silicon, micro - strip array detector of the Cooling Stor- age Ring on the Heavy Ion Research Facility in Lanzhou （HIRFL - CSR）, in this paper, based on the structural features of Xilinx 7 series FPGA chip, an improved design of logic circuit for the adder module is proposed, fast carry logic adder is employed and a new trigger judgment circuit is developed. Compared with the traditional adder circuit and the optimized, modeling analyses of structural performance and logic dead - time, the circuit was simulated and tested. The dead time of improved module is reduced to about 3 ns. Compared with oth- er types of adder circuit structures, the signal processing time of new trigger judgment circuit is reduced, and the effective acquisition rate is increased, thus, the total dead time of L1 trigger system is reduced. The design can meet the need of L1 sub - trigger system.

关 键 词：硅微条阵列探测器 死时间 现场可编程逻辑门阵列 L1触发 快速进位加法器 

分 类 号：TL8[核科学技术—核技术及应用]