用于心电采集的动态调整低功耗24位Δ-Σ ADC  

A Low Power 24-Bit Δ-Σ ADC for ECG Signal Acquisition with Dynamic Adjustment

作　　者：王湾[1] 姜汉钧[1] 徐乃昊[1] 李冬梅[1] 王志华[1] 

机构地区：[1]清华大学微电子所,北京100084

出　　处：《微电子学》2016年第2期150-154,共5页Microelectronics

基　　金：国家自然科学基金资助项目(61474070);清华大学自主科研项目(2012087960)

摘　　要：实现了一种用于心电信号采集的动态调整工作模式的低功耗24位Δ-ΣADC。采用3阶5位的调制器结构,高速模式下,SNR达到120.4dB,ENOB为19.71位;低速模式下,SNR为108.4dB,ENOB为17.71位。使用一种自适应的QRS波检测模块,ADC可以根据心电波形实时调整工作模式。针对典型心电信号,采用动态调整模式后的数据量可以压缩至非动态调整时的62.5%,平均功耗可以降低至101.5μW,是非动态调整时的66.7%。A low-power 24-bit Δ-Σ ADC was designed for ECG（electrocardiogram）acquisition with dynamic adjustment.Using a 3rd order 5-bit modulator structure,the ADC had achieved a SNR（Signal-Noise Ratio）of120.4dB,an ENOB of 19.71 bit in high speed mode,and had achieved a SNR of 108.4dB,an ENOB of 17.71 bit in low speed mode.By adding a QRS detector with dynamic adjustment,the ADC could adjust rapidly the working modes according to the wave forms of the ECG signals.As to a typical ECG signal,the amount of data with dynamic adjustment could significantly be reduced to 62.5% of the conventional ADC that had no dynamic adjustment,while the average power consumption of ADC could be reduced to 101.5μW,66.7% of the conventional ADC.

关 键 词：Δ-ΣADC 心电采集 低功耗 QRS波检测 动态调整 

分 类 号：TN792[电子电信—电路与系统]