低杂散锁相环中鉴频鉴相器与电荷泵的设计  

Design of Phase Frequency Detector and Charge Pump for Low Spur Phase Locked Loops

作　　者：李森[1] 江金光[2] 

机构地区：[1]武汉大学物理科学与技术学院,武汉430072 [2]武汉大学卫星导航定位技术研究中心,武汉430079

出　　处：《微电子学》2016年第2期228-232,共5页Microelectronics

基　　金：国家自然科学基金资助项目(41274047);广东省科技计划资助项目(2013B090500049);江苏省自然科学基金资助项目(BK2012639)

摘　　要：采用TSMC 0.18μm混合CMOS工艺,设计了一种应用在1.571GHz GNSS接收机中低杂散锁相环的鉴频鉴相器与电荷泵电路。鉴频鉴相器采用两相非重叠时钟结构和延时可控电路,实现了鉴频鉴相器的延时失配最小化和导通时间可调,在降低杂散的同时消除死区。电荷泵采用4路控制信号和1路可控充电和放电电路,有效地优化了电流失配和电荷泵电流的大小,进一步降低锁相环的杂散。测试结果表明,在电源电压为1.8V,电荷泵电流为100μA时,延时失配和充放电电流失配近似为0,杂散为-71.77dBc@16.375 MHz。A phase frequency detector（PFD）and charge pump（CP）for low spur PLL in 1.571 GHz GNSS was designed and implemented in TSMC 0.18μm mixed-signal CMOS process.A clock circuit with non-overlap two phase and a controllable delay circuit were used for PFD to minimize the delay mismatch and adjust the switch-on time.So the spur could be reduced and the dead zone could be eliminated simultaneously.To make the charging and discharging currents match and get an optimal current of CP,the CP adopted a circuit with four control signals and one controllable charging and discharging signal.Then the spur was reduced further.Results from simulation and measurement showed that the delay mismatch and current mismatch were nearly zero,the spur was-71.77dBc@16.375 MHz when it operated at 1.8V with a current of 100μA.

关 键 词：锁相环 鉴频鉴相器 电荷泵 低杂散 延时失配 电流失配 

分 类 号：TN432[电子电信—微电子学与固体电子学]