基于子树重构的三维时钟树拓扑结构优化  

Clock Tree Topology Optimization Based on Reconstructing Subtree Topology for 3D ICs

作　　者：钱晨[1] 王琴[1] 谢憬[1] 毛志刚[1] 

机构地区：[1]上海交通大学微纳电子学系,上海200240

出　　处：《微电子学与计算机》2016年第5期10-14,共5页Microelectronics & Computer

基　　金：国家自然科学基金项目(61176037)

摘　　要：传统的基于TSV的三维集成电路时钟树综合流程主要包括抽象拓扑树生成、层嵌入、布线和缓冲器插入.现有的三维时钟抽象拓扑树生成算法大多忽视了对由经典时钟拓扑树生成算法得到的抽象树结构的优化调整.对此提出了一种3D抽象拓扑树优化算法,能够调整特定子树的根节点位置从而优化抽象拓扑树结构.同时,把该优化算法整合到传统的时钟树综合流程中.仿真实验结果表明优化算法可以将三维集成电路时钟网络的总线长减小最多4.56%,而时钟延迟最多可减少14.67%.The traditional TSV-based 3D clock tree synthesis （3D CTS） flow mainly concludes abstract topology generation, embedding, routing and buffering. The classic 3D clock tree abstract topology generation algorithms ignore the adjustment for the generated topology after the first step. In this paper, we propose a clock tree topology optimization algorithm, the LMOR algorithm, for reconstructing the structure of some specific subtrees in the generated 3D clock tree abstract topology and relocating the position of the roots of these subtrees. The simulation results show that the total wirelength and delay can be reduced by up to 4. 56% and 14.67%.

关 键 词：三维集成电路 三维时钟树综合 硅通孔 抽象拓扑树 

分 类 号：TN4[电子电信—微电子学与固体电子学]