去斜率信号的极坐标格式成像算法的FPGA实现  

Realization of FPGA-based polar format imaging algorithm used for dechirp signal

作　　者：丁勇[1] 朱岱寅[1] 段化军[1] 石佳宁[1] 

机构地区：[1]南京航空航天大学电子信息工程学院雷达成像与微波光子技术教育部重点实验室,江苏南京211106

出　　处：《现代电子技术》2016年第9期6-11,共6页Modern Electronics Technique

基　　金：国家自然科学基金(61301212);航空科学基金(20132007001;20132052030);江苏省研究生培养创新工程(SJLX_0131);中央高校基本科研业务费专项资金资助项目;中国博士后科学基金(2012M511750);国防基础科研计划(B2520110008);江苏高校优势学科建设工程资助项目;江苏省产学研联合创新资金前瞻性研究项目(BY2014003-05)

摘　　要：针对机载合成孔径雷达(SAR)实时处理需求,传统的数字信号处理器(DSP)实现方式由于性能、功耗以及可靠性等原因,已经越来越不能满足实时性的要求,因此设计并实现了一种基于现场可编程门阵列(FPGA)的聚束SAR极坐标格式(PFA)算法,主要用于处理去斜率信号。该设计中采用两次Chirp-Scaling操作代替复杂的二维插值过程,提高了算法效率。由于雷达成像算法处理时常分为距离向、方位向分步实现,该次设计采用时分复用的方式,在处理时间无明显增加的情况下,极大的减少了FPGA的资源使用。该设计采用Xilinx公司KC705开发板进行验证,经测试当系统时钟频率工作在200 MHz时,处理单精度浮点8 192×8 192像素点SAR图像的时间约为8 s。Since the traditional DSP is unable to meet the real-time requirement due to the reasons of performance,power consumption and reliability,a FPGA-based polar format algorithm（PFA）for beaming airborne synthetic aperture radar（SAR）was designed and implemented to deal with the dechirp signal for the real-time processing demand of SAR. The twice Chirp-Scaling operation was used in this design to replace the complicated two-dimensional interpolation process to improve the efficiency of the algorithm. The step-by-step implementation of distance and azimuth directions is usually adopted in radar imaging algorithm.The way of time division multiplexing is adopted in this design to greatly reduce the resource usage of FPGA when a little processing time is increased. The design was verified on KC705 development board made by Xilinx. It approximately takes 8 s to process the SAR image of 8 192×8 192 single precision floating point pixels when the system clock frequency works at 200 MHz.

关 键 词：合成孔径雷达 去斜率信号 极坐标格式算法 现场可编程门阵列 

分 类 号：TN953.434[电子电信—信号与信息处理]