一种基于电压窗口技术的超低功耗SAR ADC  

An Ultra-Low Power SAR ADC with Voltage Window Technique

作　　者：汪正锋[1] 宁宁[1] 吴霜毅[1] 杜翎[1] 蒋旻[1] 闫小艳[1] 王伟[1] 

机构地区：[1]电子科技大学电子薄膜与集成器件国家重点实验室,四川成都610054

出　　处：《电子学报》2016年第1期211-215,共5页Acta Electronica Sinica

基　　金：国家自然科学基金(No.61404022);中央高校基本科研业务费(No.ZYGX2012Z007)

摘　　要：本文提出了一种应用于生物医学的超低功耗逐次逼近型模数转换器(SAR ADC).针对SAR ADC主要模块进行超低功耗设计.数模转换(DAC)电路采用vcm-based以及分段电容阵列结构来减小其总电容,从而降低了DAC功耗.同时提出了电压窗口的方法在不降低比较器精度的情况下减小其功耗.此外,采用堆栈以及多阈值晶体管结构来减小低频下的漏电流.在55nm工艺下进行设计和仿真,在0.6V电源电压以及10k S/s的采样频率下,ADC的信噪失真比(SNDR)为73.3d B,总功耗为432n W,品质因数(FOM)为11.4f J/Conv.An ultra-lowpower successive approximation register analog-to-digital converter for biomedical application is proposed. Many ultra-lowpower design methods are utilized for its main modules. The digital-to-analog converter（ DAC）employs a vcm-based and split capacitor array structure to cut down the total capacitance,so as the power consumption. Voltage windowtechnique is used to decrease the power consumption of the comparator without sacrificing its accuracy. Furthermore,stack forcing and multi-Vt design approaches are used to reduce the leakage current under lowfrequency. The proposed SAR ADC is designed and simulated in 55 nm process. With 0. 6V power supply and 10 k S / s sampling rate,the ADC achieves a signal-to-noise-and-distortion-ratio（ SNDR） of 73. 3d B. The total power consumption is 432 n W and the figureof-merit（ FOM） is 11. 4f J / Conv.

关 键 词：模数转换器(ADC) 逐次逼近寄存器(SAR) 电压窗口 超低功耗 

分 类 号：TN402[电子电信—微电子学与固体电子学]