基于锁相环的遥感相机采样电路设计与优化  

Design and Optimization of Sampling Circuit in Remote Sensing Camera Based on PLL

作　　者：梁楠[1] 李涛[1] 吴淞波[1] 

机构地区：[1]北京空间机电研究所,北京100094

出　　处：《航天返回与遥感》2016年第2期66-73,共8页Spacecraft Recovery & Remote Sensing

基　　金：国家重大科技专项工程

摘　　要：高分辨率时间延迟积分电荷耦合器件(TDICCD)遥感相机成像系统设计中,通道数量、高频时钟品质、高速数据传输误码率与相机小型化设计已经成为相互制约的矛盾。目前,为了减小系统体积质量、提高图像信噪比,将采样电路放入相机主体的焦平面附近是目前遥感系统小型化的主要趋势。因此,在相机主体与图像处理器之间,高速数据传输和高速时钟抖动是采样电路的主要设计难题。文章设计了一套基于锁相环(PLL)的高速采样电路,抑制了高速时钟抖动,消除了相位差;设计了一种超前滞后滤波器作为锁相环电路的环路滤波器。通过仿真和实测分别得到了滤波器电路的相位裕度和锁定时间等参数;同时在电路板布局布线时,通过合理地切割地平面、优化时钟的走线,抑制了模数混合部分的量化噪声。电路中使用了串行传输技术实现高速大数据量的传输;最后,文章中对误码率和图像信噪比进行实测,测试结果满足实际工程应用的需求。该设计同传统采样电路相比较,在尺寸、质量、数据传输率、图像信噪比等方面均有较大优化。In the imaging system of the high resolution TDICCD remote sensing camera,the number of channels, the quality of high-frequency clock and the errors of high-speed data transmission have become an important factor limiting the miniaturization of camera. Currently, sampling circuit is placed near the focal plane in order to improve the system volume, weight and SNR. Therefore, the high-speed clock jitter and the high-speed transmission are becoming the major design challenges of the sampling circuit. In this paper, a high-speed sampling circuit based on PLL is adopted to suppress the high-speed clock jitter and eliminate the phase difference. It uses a lead-lag filter as the PLL loop filter. The Phase margin and the lock time of the filter are achieved through simulation and test. At the same time, quantization noise is suppressed through optimizing clock and cutting the ground plane in PCB. The high-speed serial interface can be used for large data transmission. The BER and the SNR is calculated through the digitalized images and meet the requirements of the project. Compared with the traditional sampling circuit, the high-speed sampling circuit is greatly optimized in size, weight, data transmission rate and SNR.

关 键 词：时间延迟积分电荷耦合器件 时钟抖动 信噪比 锁相环 误码率 电路设计 遥感相机 

分 类 号：TN401[电子电信—微电子学与固体电子学]