基于3D-Mesh互连网络的粗粒度逻辑阵列研究  

Research on 3D-Mesh topology interconnection network in the coarse grained reconfigurable cryptographic logic array

作　　者：赵宗国[1] 李伟[1,2] 戴紫彬[1] 耿九光[3] 

机构地区：[1]解放军信息工程大学 [2]复旦大学专用集成电路与系统国家重点实验室 [3]71315部队

出　　处：《电子技术应用》2016年第5期27-31,共5页Application of Electronic Technique

基　　金：国家自然科学基金(61404175)

摘　　要：提出了一种3D-Mesh拓扑互连网络结构,其支持动态可重构配置,数据路径位宽为32 bit。基于该3D-Mesh拓扑互连网络结构,设计了一种拥有48个RPE(Reconfigurable Process Element)和16个RSE(Reconfigurable Storage Element)的异构粗粒度逻辑阵列(Isomerism Coarse-Grained Reconfigurable Array,ICGRA)。基于COMS 55 nm工艺库进行后端设计,ICGRA总面积为28.52 mm2。同时在300 MHz系统时钟、1.08 V Vcc电压、室温条件下系统总功耗为2.88 W。其中3D-Mesh拓扑互连网络面积占系统总面积的3.8%,功耗占系统总功耗的7%。与相关设计对比,该结构动态重构速率提高2倍～60倍。且采用该3D-Mesh拓扑网络之后,运算单元利用率也大幅度提高。This paper presents a 3D-Mesh interconnection network structure with 32 bit data path, which can support dynamic reconfiguration. Based on the 3D-Mesh topology interconnection network structure, a new type of isomerism coarse-grained reconfigurable array with 48 RPE and 16 RSE is designed. Based on the 55 nm COMS process library to design, the total area of ICGRA is 28.52 mm2. At the same time, total power consumption of the system is 2.88 W@300 MHz ＆ 1.08 V Vcc in the room temperature. The network area of 3D-Mesh topology is 3.8 % of the total area of the system, and the power consumption is 7 % of the total system power. In comparison with the related classes, the structure dynamic reconstruction rate is 2～60 times higher. After using the 3D-Mesh topological network, the utilization rate of the arithmetic unit is also improved greatly.

关 键 词：粗粒度逻辑阵列 片上网络 3D-Mesh 可重构 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构]