基于分布式模拟机制的片上网络硬件模拟系统  

Hardware Simulation System for Network on Chip Based on Distributed Simulation Mechanism

作　　者：彭毅[1] 安虹[1] 金旭[1] 程亦超 迟孟贤 孙荪[1] 

机构地区：[1]中国科学技术大学计算机科学与技术学院,合肥230027

出　　处：《计算机工程》2016年第5期71-79,共9页Computer Engineering

基　　金：国家自然科学基金资助项目(60970023);国家"973"计划基金资助项目(2011CB302501);国家"863"计划基金资助项目(2012AA010902;2012AA010901)

摘　　要：针对基于现场可编程门阵列的DART模拟器可扩展性较差和模拟精度较低的问题,提出一种硬件友好的分布式模拟机制。该机制在模拟中采用隐式同步方法,以节点内计数器和节点间缓冲队列取代集中式控制器,将时序同步和计数任务交给每个节点自行处理,从而提高模拟速度。基于该机制,设计并实现片上网络硬件模拟系统。实验结果表明,该系统能达到与业界权威BookSim模拟器同级别的模拟精度,模拟速度可达BookSim模拟器的200倍,相比DART模拟器能获得21%的速度提升,并且具有较好的扩展性。Aiming at the problems of poor scalability and low precision of DART simulator based on Field Programmable Gate Array （FPGA）, this paper proposes a hardware-friendly distributed simulation mechanism. This mechanism uses implicit synchronization method, and replaces the centralized controller with intra-node counters and inter-node buffer queues. In this way, timing synchronization and counting can be handled by each node, which improves the simulation speed. Based on this mechanism, a Network on Chip （NoC） simulator is designed and implemented. Experimental results demonstrate that this simulator can achieve similar accuracy to widely-used BookSim simulator software ones and gain 200-fold speedup. Compared with DART simulator, it accelerates simulation speed by 21% at most and achieves better scalability.

关 键 词：片上网络 分布式模拟 现场可编程门阵列 多核处理器 时钟精确 动态路障同步 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]