基于现场可编程门阵列并行频率源的改进方法  

Improved Method of Parallel DDS Based on FPGA

作　　者：徐跃[1] 简金蕾[1] 任宏滨[1] 连可[2] 吉阳[1] 

机构地区：[1]空军工程大学防空反导学院,陕西西安710051 [2]中国电子科技集团公司第十研究所,四川成都610036

出　　处：《探测与控制学报》2016年第2期82-87,共6页Journal of Detection & Control

摘　　要：针对传统直接数字频率合成(DDS)电路中相位累加器与波形查找表的工作频率与高速数模转换器(DAC)采样频率不匹配的问题,提出了基于现场可编程门阵列(FPGA)并行频率源的改进方法。该方法采用改进的8路并行DDS电路有效地扩展了DDS电路的输出带宽;基于并行DDS结构,利用FPGA和高速DAC生成了不同调制模式下的通信信号,并在Vivado2014.2环境下进行测试。实验表明:该设计具有结构简单、易于实现、分辨率高等特点,可用于雷达、电子对抗领域中宽频带高分辨率信号的产生。Aiming at the disagreement among the frequency of phase accumulator,wave look-up table,and the frequency of high speed DAC in traditional DDS,an improved method of parallel DDS based on FPGA was put forward.The method took use of improved paralled DDS circuit of 8channels to design,which expended output band effectively.Different modulation mode communication signals were generated via FPGA and high speed DAC based on parallel DDS.It was performed under the environment of Vivado 2014.2.The testing results showed this design was of simple construction,easy implementing and high frequency,which could be used in wide band high frequency signal generation.

关 键 词：并行直接数字频率合成 波形查找表 现场可编程门阵列 调制 高速数模转换器 

分 类 号：TN911.7[电子电信—通信与信息系统]