基于SystemC的可重构阵列处理器模型  

Reconfigurable Array Processor Modeling Based on SystemC

作　　者：蒋林[1] 王杏军 刘镇弢[1] 宋辉[1] 

机构地区：[1]西安邮电大学电子工程学院,陕西西安710121

出　　处：《西安邮电大学学报》2016年第3期73-78,共6页Journal of Xi’an University of Posts and Telecommunications

基　　金：国家自然科学基金资助项目(61272120);陕西省自然科学基金资助项目(2015JM6326);陕西省科技统筹创新工程基金资助项目(2016KTZDGY02-04-02)

摘　　要：基于可重构技术以及SystemC的体系结构建模特点,构建一种基于SystemC的可重构阵列处理器模型。采用模块化的SystemC系统模型分别对指令传输模块、处理元模块以及邻接互连模块建模,构成32×32的可重构阵列处理器。通过指令传输模块实现局部和非局部两种单指令多数据模式的快速切换,使用邻接互连模块完成处理元间的通信。对建立的模型进行仿真验证,同时将高效视频编解码标准中视频算法映射到该模型上。仿真结果表明,该模型搭建正确,能够实现视频编解码标准中视频算法的并行化映射。Based on the reconfigurable technology and the feature of SystemC architecture modeller,a reconfigurable array processor modelling based on SystemC is proposed.A model of reconfigurable array processor with 32×32 is built by building instruction transmission module,processing element module and adjacent interconnect module by using the modular SystemC system model design method.The model uses the instruction transmission module to achieve the fast switching of the local single instruction multiple data and the non-local single instruction multiple data mode,and then the adjacent interconnection module is used to complete the communication between the processing elements.Once the modeller is set up,simulation and verification are carried out,and the new generation video coding standard is mapped to the modeller.Simulation results show that the system modeller is correct and can achieve the parallel mapping of the new generation of efficient video codec standard video algorithm.

关 键 词：阵列处理器 可重构技术 SYSTEMC 体系结构建模 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]