Intel64体系结构的数据预取机制及效果  

Mechanism and Capability of Data Prefetching in Intel64 Architecture

作　　者：董钰山 李春江[1] 

机构地区：[1]国防科学技术大学计算机学院软件研究所,长沙410073

出　　处：《计算机科学》2016年第5期34-41,共8页Computer Science

基　　金：国家自然科学基金项目:多核多线程处理器SIMD扩展的编程模型及编译优化关键技术研究(61170046);863计划项目:面向国产飞腾处理器的并行程序综合优化系统(2012AA010903)资助

摘　　要：数据预取是为缓解微处理器与DRAM之间速度差异而出现的隐藏访存延迟的方法。当前Intel各系列处理器都采用多种预取机制来加速数据和代码向Cache的移动,从而提升程序的性能。通过对Intel64体系结构存储层次的分析,剖析了X86/X64体系的数据预取机制,包括硬件预取和软件预取,并且分析了编译器对软件预取机制的支持。最后测试了Intel64体系结构数据预取对科学计算程序中紧嵌套循环性能的影响,总结出了影响数据预取有效性的几个因素。此项工作对在Intel平台上进行循环数组预取优化有指导意义。Data prefetching is an approach to reducing cache miss latencies,which can appropriately fill the speed gap between the microprocessor and DRAM.Recently,Intel processor families employ several prefetching mechanisms to accelerate the movement of data or code to Cache,and improve performance.By a brief analysis of the memory hierarchy of Intel64 architecture,data prefetching mechanism of X86/X64 architecture,including hardware prefetching and software prefetching,was deeply dissected,and then the compiler support for software prefetching mechanism was analyzed.After testing the performance of data prefetcher of Intel64 architecture for nested loop,we concluded several factors affecting the effect of data prefetching.These works provide a valuable contribution for the research and development of the loop-array-prefetching optimization on the Intel platform.

关 键 词：INTEL 64 CACHE 硬件预取 软件预取 GCC ICC 

分 类 号：TP314[自动化与计算机技术—计算机软件与理论]