DOIND： a technique for leakage reduction in nanoscale domino logic circuits  

作　　者：Ambika Prasad Shah Vaibhav Neema Shreeniwas Daulatabad 

机构地区：[1]Electronics & Telecommunication Engineering Department, IET-Devi Ahilya University, Indore-452017, India [2]Electrical Engineering Department, Indian Institute of Technology, Bombay-400076, India

出　　处：《Journal of Semiconductors》2016年第5期69-77,共9页半导体学报（英文版）

摘　　要：A novel DOIND logic approach is proposed for domino logic, which reduces the leakage current with a minimum delay penalty. Simulation is performed at 70 nm technology node with supply voltage 1V for domino logic and DOIND logic based AND, OR, XOR and Half Adder circuits using the tanner EDA tool. Simulation results show that the proposed DOIND approach decreases the average leakage current by 68.83%, 66.6%, 77.86% and 74.34% for 2 input AND, OR, XOR and Half Adder respectively. The proposed approach also has 47.76% improvement in PDAP for the buffer circuit as compared to domino logic.A novel DOIND logic approach is proposed for domino logic, which reduces the leakage current with a minimum delay penalty. Simulation is performed at 70 nm technology node with supply voltage 1V for domino logic and DOIND logic based AND, OR, XOR and Half Adder circuits using the tanner EDA tool. Simulation results show that the proposed DOIND approach decreases the average leakage current by 68.83%, 66.6%, 77.86% and 74.34% for 2 input AND, OR, XOR and Half Adder respectively. The proposed approach also has 47.76% improvement in PDAP for the buffer circuit as compared to domino logic.

关 键 词：deep submicron DOIND logic domino logic EVALUATION precharge subthreshold leakage 

分 类 号：TN791[电子电信—电路与系统] TN305.7