基于FPGA的高速高阶FIR滤波器的频域改进方法  

Frequency domain improvement method for high-speed and high-order FIR filter based on FPGA

作　　者：郭晓伟[1,2] 陈钟荣[1,2] 夏利娜[1,2] 

机构地区：[1]中国气象局气溶胶-云-降水重点开放实验室,江苏南京210044 [2]南京信息工程大学大气物理学院,江苏南京210044

出　　处：《现代电子技术》2016年第11期55-58,62,共5页Modern Electronics Technique

摘　　要：为了提高现场可编程门阵列(FPGA)设计的超高阶有限单位冲击响应(FIR)滤波器对数据进行实时处理,提出了一种改进的频域设计FIR滤波器方法。针对频域处理卷积运算时,由于补零耗时造成数据无法实时处理这一问题进行了改进。首先将长序列分成固定长度的子序列,将原来利用一个(快速傅里叶变换)FFT IP处理子序列的常规方案改为利用两个FFT IP进行运算,通过控制子序列输入两个FFT IP的时间差,便可以利用重叠相加法的原理,将子序列卷积之后的结果直接相加,便可得到卷积结果,从而达到信号实时处理的目的。实例仿真计算表明,提供的频域实现方法不仅能降低FPGA资源消耗,还能够消除现有技术中的补零延迟现象,提高了处理速度。To implement the real-time data processing of using ultrahigh-order finite impulse response（FIR）filter designed with field-programmable gate array（FPGA）,an improved method of FIR filter designed in frequency domain is put forward. The problem that the data can′t be processed in real time,caused by the zero padding time consumption,was solved for processing the convolution operation in frequency domain. A long sequence is divided into the subsequences with fixed length,and then the subsequence is processed with two FFT（fast Fourier transform）IPs instead of the conventional scheme with one FFT IP. By controlling the time difference between the two input FFT IPs,the principle of overlapping addition method can be utilized to add the results to obtain the convolution result after subsequences convolution,thus real-time processing of the signal is achieved.The instance simulation results show that the proposed frequency domain implementation method can reduce the FPGA resource consumption,eliminate the zero padding delay in the available technologies,and improve the processing speed.

关 键 词：FIR滤波器 快速傅里叶变换 FPGA 频域改进方法 

分 类 号：TN713-34[电子电信—电路与系统]