基于协议控制器的DDR3访存控制器的设计及优化  

Design and Optimization of a DDR3 Memory Controller with Protocol Controller

作　　者：陈胜刚[1] 付兴飞 曾思[1] 

机构地区：[1]国防科学技术大学计算机学院,湖南长沙410073

出　　处：《微电子学与计算机》2016年第6期6-10,共5页Microelectronics & Computer

基　　金：国家自然科学基金项目(61402500)

摘　　要：为了完成SoC系统中片外DDR3存储器高效访问,实现了基于协议控制器的DDR3访存控制器.针对SoC系统层访问事务属性与DDR3存储器突发访问属性要求之间的不匹配问题,设计了一种访问请求平滑处理机制,充分利用协议控制器的DDR3访问命令缓冲,用更少的DDR3存储器访问请求完成SoC上层读写事务,提高了整个DDR3访存控制器的访问效率.采用Verilog语言完成了逻辑设计和物理实现,并采用人工综合激励的方法对访问请求平滑机制进行了评估,实验证明该优化机制可对DDR3访存控制器实现有效加速.A DDR3 Memory controller with protocol controller is implemented to efficiently access the off-chip DDR3 memory in a SoC system.Considering the unmatched property between the SoC system level read-write transactions and the DDR3 SDRAM burst access requirement,a memory transaction smoothing mechanism is implemented in the DDR3 memory controller,which makes well use of the protocol controller＇s DDR3 SDRAM memory command pipeline and can reduce the times of the actual off-chip SDRAM access to improve efficiency of the entire DDR3 memory controller.Verilog model and physical implementation of the memory controller are carried out.Evaluation based on synthetic stimulus show that the smoothing mechanism can improve the efficiency of the DDR3 memory controller.

关 键 词：DDR3 访存控制 请求平滑 

分 类 号：TP331.2[自动化与计算机技术—计算机系统结构]